LithoTalk

[Ugur_FZJ]

Hi,

Surfing in the internet to find an answer for my problems with a process which is part of my work, I landed here . I'm trying to structure a Pt layer into 6.6x6.6 um squares on 5mmx5mm chips. Later, these are to be covered by a dielectric passivation material. While the passivation will cover the entire chip with the exception of the bond pads, the Pt-squares must keep their shape, and especially have smooth edges. Currently, I'm facing several problems with the process:

1) Due to the small size of the chips, the photoresist I use (AZ nLOF 2020) tends to pile up at the corners and the edges of the 5mmx5mm chips, which keep the mask from establishing a real hard contact with the chip surface in the center (The Pt-squares are in the center, so this is the really important part of the chip for me during the exposure)

2) After post-exposure baking, development and metal deposition (currently we use sputtered Pt due to its smoother surface than the e-beam evaporated one), the lift-off takes place in NMP. During that however, the Pt layer between the individual Pt-squares sometimes tends to stick on the chip surface, even though it was supposed to come off due to the resist beneath it (The distance between the squares is 12 um wide).
Sometimes, even if this layer comes off, the edges of the Pt-squares that remain on the chip are very rugged. Our latest SEM images show little peaks of Pt standing right at these edges and facing up, almost at a 90 deg. angle to the chip surface.

I'm looking forward to hear your thought and ideas on these problems - I guess many of you had similar stuff to deal with .

Best Regards

Ugur